Functional verification of digital hardware design at register transfer level (RTL) is important in the design cycle of an integrated circuit design. Despite the emphasis on verification, typically seventy percent (70%) or more of integrated circuit design tape-outs require rework or redesign and another spin or re-spin through the design cycle. One cause of the rework in the initial IC design is the logic or functional defects that otherwise could have been caught at a functional verification stage of the IC design.
Thus, verification of an IC design prior to manufacture of the design is important to avoid rework and redesign and lower overall costs of integrated circuit designs.